Synthesis of Controllers from Interval Temporal Logic Specication

We present a method which accepts Interval Temporal Logic (ITL) formulas as specication and automatically generates state machines. Since ITL is based on intervals and their sequences, we can easily describe both concurrent and serial behaviors by specifying behaviors inside intervals and sequences among them. ITL formulas are expanded into the ones for the cases that the present state is the nal state of the current interval and those for the cases that there is next state in the current interval, which can be easily converted into state machines, by tabulated rules for temporal operators. The specica-tion in ITL can also be used as a constraint for a (possibly non-deterministic) state machine which is an abstraction for an existing sequential circuit. In that case, the nal synthesized circuit satises the properties both in ITL and the original state machine, which can be useful for redesign or engineering change. The generated state machines can be further processed by logic synthesizer, such as SIS, and transformed into synchronous/asynchronous sequential circuits. We present experimental results and show the usefulness of our method.